Chip Scale Review: "Comparison between wet and dry silicon via reveal in 3D backside processing"
June 14, 2016
Full Article: http://fbs.advantageinc.com/chipscale/may-jun_2016/#48/z
This paper compares imec's current wet chemical via reveal process of record, based on the selective TMAH chemistry, with SPTS’s dry etch via reveal, based on an SF plasma. State-of-the-art metrology has been used to image large arrays of revealed TSVs. Data on nail height control and uniformity, liner selectivity and surface roughness are presented and discussed.
Authors: Dave Thomas et al. (SPTS Technology) and Anne Jourdain et al. (imec)
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