Solving the Plasma Dicing Puzzle (21 March 2018)
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This webinar was presented live on Wednesday 21st March. To replay the recording, CLICK HERE (Registration will be required)
In the semiconductor field there is a strong trend towards miniaturization driven by smartphones, tablets, PCs, TVs, and wearables, pushing the industry to develop devices with more functionalities packed into a smaller form factor.
Plasma dicing is an enabling technology for singulating small, thin or fragile die, when conventional mechanical or laser dicing becomes too slow, costly or even technically impossible. Examples of plasma singulated die are appearing in leading consumer devices, proving the technology is now being commercially adopted, and yet manufacturers wishing to exploit the undoubted advantages of plasma dicing need to consider many integration factors.
Part I - Overview of Dicing Technologies and Future Trends - Yole Développement
In the first part of this webinar, Yole Développement gave an overview and its vision of the key dicing technologies across CMOS Image Sensors, MEMS & Sensors, Power devices as well as RFID devices, highlighting trends of the dicing technologies: technology evolution analysis, and what is expectations for the next few years.
Part II - Integrating Plasma Dicing into Volume Production - SPTS Technologies
SPTS then discussed process integration considerations, including cost implications, the influence of tape selection, and end-point options for process control in volume production. Of topical note is the combination of LASER and plasma for quicker avenues to adoption, this session covered how the plasma etch can accommodate the side effects of LASER grooving, showing examples of this approach and the benefits that can be achieved.
Designing in plasma dicing from the outset of a device life cycle is perhaps the only way to realize all of the benefits that plasma dicing can provide. However, this presentation showed novel approaches which have proven that plasma dicing can be immediately adopted into existing process flows and some significant advantages can be realized, namely improved device quality and strength.
Plasma dicing in all its forms is still in the early stages of adoption for volume production. However, the latest processing equipment is now available on a full cluster production platform capable of automatically handling 300mm wafers on 400mm tape frames ready for the wide-scale introduction of this technology. Looking forward, this presentation gave an brief update on SPTS's dicing activities with non-silicon materials, and illustrate that plasma dicing is here to stay and how future device designs won’t be possible without it.
Technology & Market Analyst, Yole Développement
Amandine Pizzagalli is a Technology & Market Analyst at Yole Développement (Yole). Amandine is part of the development of the Advanced Packaging & Semiconductor Manufacturing Business Unit of Yole with the production of reports and custom consulting projects. She is in charge of comprehensive analyses focused on semiconductor equipment, materials and manufacturing processes.
Previously, Amandine worked as Process engineer on CVD and ALD processes for semiconductor applications at Air Liquide. Amandine was based in Japan during one year to manage these projects.
Amandine is graduated in Electronics from CPE Lyon (France), with a technical expertise in Semiconductor & Nano-Electronics and has a master focused on Semiconductor Manufacturing Technology, from KTH Royal Institute of Technology (Sweden).
She has spoken in numerous international conferences and has authored or co-authored more than 10 papers.
Etch Product Manager, SPTS Technologies
Richard Barnett is Etch Product Manager at SPTS, an Orbotech company, and has 20 years’ experience in the semiconductor and electronics manufacturing industries. Prior to his current role, Richard worked in product management and as a process engineer at both Aviza and Surface Technology Systems (STS), prior to their merger to form SPTS. Earlier in his career, Richard worked at Pure Wafer plc, Lucas Aerospace and European Semiconductor Manufacturing, and began his career with LG Semiconductor as a member of their first overseas fab engineering team in the diffusion/wet-etch process group.
Richard holds a Bachelor’s degree in Engineering for Material Engineering and Electronics from the University of Nottingham, has published technical articles related to silicon DRIE, and has delivered multiple presentations on wafer processing technologies