Plasma Dice After Grind

Wafer dicing, or die singulation, is generally carried out using conventional blade, or laser, technology. However, these methods have inherent limitations which can be overcome by using dry etch techniques.  With more than 1100 modules in use for DRIE Si etching, SPTS is widely accepted as the market leader in silicon DRIE for MEMS and Advanced Packaging; we are now bringing that capability to wafer dicing.
 
Plasma dicing can either occur before grinding (DBG - Dice Before Grind) or after grinding (DAG – Dice After Grind). 
 
There are many benefits when using plasma etch to separate die.  SPTS’s DRIE technology allows designers to reduce dicing lane widths, remove damage exclusion zones and adopt flexible approaches to die shape and layout.  All of which increases the number of die that can be arranged on a wafer. 
 
Plasma dicing is a parallel activity, rather than a serial activity as with blade or laser techniques. Therefore, as the number of die and associated dicing lanes increases, the throughput gap between mechanical and plasma singulation widens.  Furthermore, by eliminating the abrasion, vibration and heat generation aspects of mechanical singulation techniques, die singulated by plasma etch will have greater die strength and likely to have increased reliability and lifetimes.  All of this adds up to significant gains in terms of throughput, die output and yields.
 
Example of alternative die shapes
Bumped die on tape singulated using plasma dicing
 
In DAG schemes, the thinned wafer is placed onto taped frames and the die are singulated by etching through to the tape.  This method requires careful process control to prevent notching at the silicon-tape interface, and tape damage on exposure to the plasma. SPTS has a patented end-point detection solution, Sentinel™, capable of indicating the point at which the tape is reached, even for extremely low exposed silicon areas.  This enables the process conditions to be adjusted during the short over-etch period used to complete the etch across the whole wafer.  To further help eliminate notching, SPTS has a patented solution which uses RF pulsing, originally developed for etching MEMS devices on SOI wafers. This prevents the build-up of charge on the non-conducting tape and reduces deflection of ions into the sidewall.  Recent investigation has proved that reduced notching equates to higher die strength.  In fact, plasma etched die processed without this notch control are weaker than mechanically diced samples[1].
 
SPTS has successfully demonstrated plasma dicing using a variety of commonly used tapes. 
 
The SPTS system recommended for DAG is our Mosaic™ fxP Rapier, which is compatible with framed wafers up to 300mm.
Key Features of the Mosaic™ fxP Rapier:
  • Frame compatible end effectors
  • 6 process module positions
  • Alignment of wafer (on frame) for etch process repeatability
 
 
[1] R. Barnett, D. Thomas, O. Ansell, J, Carpenter, W. Worster, G. Ragunathan “Improving Device Yields and Throughput using Plasma Dicing” presented at IWLPC2015