SPTS provides advanced wafer processing solutions to the world's leading semiconductor device manufacturers and research institutions. Through an ongoing program of research and development and collaborative development with customers and industry consortia, SPTS is able to contribute to the advancement of the global semiconductor industry.

We understand the requirement for collaboration in order to propel industry advancements and opportunities, and we work with a number of leading research institutes around the world, including: imec (Belgium), Fraunhofer IZM (German), CEA-Leti (France), IME / A*STAR (Singapore), Swansea University  (UK), and Cardiff University (UK).

The following are some examples of SPTS's collaborative R&D projects.

HEMAN V: High Efficiency MANufacturing of VCSELs

In March 2017, SPTS partnered with the Compound Semiconductor Centre, Swansea University and Cardiff University on a 12-month UK Government-funded project to improve/develop various processes, including ICP mesa etching from SPTS, for high volume production of GaAs/AlGaAs VCSELs on 150mm substrates.

Read More: HEMAN V: High Efficiency MANufacturing of VCSELs


In 2015, SPTS and imec began developing a highly accurate, short cycle-time dry silicon removal and low temperature passivation solution for through-silicon via-middle processing and thinning of the top-wafer in wafer-to-wafer bonding.

Initial results of this work were published in a paper at ECTC2016 and can be downloaded here.

Read more: Imec and SPTS Technologies Collaborate on Critical Processes for 3D IC Wafer Stacking


In 2014, SPTS and CEA-Leti in Grenoble, France, entered an agreement to develop 3D-TSV technologies. The agreement builds on the long established relationship between the partners who have already collaborated in the past, particularly on the development and optimization of an advanced MOCVD TiN barrier for high aspect ratio TSV.

Read more: SPTS Technologies and CEA-Leti and Nanoelec RTI collaborate on 3D-TSV Technology


In 2013, SPTS and imec, a world-leading nanoelectronics research center  announced a joint partnership to further advance micro- and nanosized components for BioMEMS, using SPTS’ Rapier silicon deep reactive ion etching (Si DRIE) technology.

Read more: http://www.analog-eetimes.com/news/imec-spts-team-biomems

A* IME High Density FOWLP Consortium

A*STAR’s Institute of Microelectronics (IME), together with Amkor Technologies, NANIUM S.A, STATS ChipPAC, NXP Semiconductors, GLOBALFOUNDRIES, Kulicke & Soffa, Applied Materials, Inc., Dipsol Chemicals, JSR Corporation, KLA-Tencor, Kingyoup Optronics, Orbotech and Tokyo Ohka Kogyo have formed a High-Density Fan-Out Wafer Level Packaging (FOWLP) consortium to extend FOWLP capabilities for applications in devices such as smart phones, tablets, navigation tools and gaming consoles.

Read more: Click here


The InforMed project represents an investment of >€58 million. Led by Philps Electronics Nederlands it involved 39 different companies from 10 countries including SPTS, Micronit, Okmetic, Ipdia, Fraunhofer and others.  InForMed is an ECSEL JU project and is co-funded by grants from Belgium, Finland, France, Germany, Great Britain, Ireland, the Netherlands, Spain, Sweden and Switzerland.

InForMed will establish a pilot line for micro-fabricated medical devices that:

  • encompasses the complete trajectory from micro-fabrication to assembly and “smart catheter” fabrication.
  • brings together key industrial and academic players in a manufacturing ecosystem
  • enables optimal use of European technologies and competencies.

The pilot line will be demonstrated by a number of innovative products for hospital and home healthcare.

Click here for case studies

SPTS has secured over €130,000 to work on two Horizon 2020 projects aiming to break new ground in semiconductor technologies and pilot innovative new medical devices.

Read more: http://informed-project.eu/ 

June 2015 - June 2018

A* IME MEMS III Consortium

A*STAR’s Institute of Microelectronics (IME) has launched its third consortium to develop cutting-edge micro-electro-mechanical systems (MEMS) technologies. This would allow MEMS sensor devices to achieve better performance, higher power efficiency and smaller form factor.  

The MEMS Consortium III comprises leading industry members Applied Materials, Coventor, Delta Electronics, GLOBALFOUNDRIES, InvenSense, SPTS Technologies, Standing Egg, ULVAC, Inc., Veeco and an electronics company. It will draw on IME’s expertise in MEMS sensors and process platform capabilities to develop industrial-grade inertial sensors and pressure sensors for adoption into a wide range of products and applications, such as electronic stability control, asset tracking, unmanned aerial vehicles, automotive and wearable devices. To achieve this, they will focus on bridging the gaps in performance, cost and size between existing industrial-grade inertial sensors and current MEMS sensors. 

Read more: https://www.a-star.edu.sg/ime/INDUSTRY/INDUSTRY-CONSORTIA.aspx

June 8th 2016


The project PowerBase receives funding from the Electronic Component Systems for European Leadership Joint Undertaking (ECSEL JU) under grant agreement No 662133. Coordinated by Infineon Tech. Austria the project involves 39 partners from 9 countries such as EpiGaN, Siltronic, Plansee and SPTS. 

The Innovation Action (IA) project “PowerBase” will follow a holistic vertical approach from material research across the entire value chain to advanced systems and aims to provide significant impact to essential technologies and key applications.

SPTS has secured over €130,000 to work on two Horizon 2020 projects aiming to break new ground in semiconductor technologies and pilot innovative new medical devices. 

Click here to read more. 

At over €70 billion Horizon 20201 is the largest ever European Union (EU) research and innovation programme and is providing real opportunities for Welsh organisations to be at the forefront of research and innovation and to collaborate with leading organisations across Europe and the world. Horizon 2020 is ‘open for business’, with successful applications made whilst the UK is part of the EU protected by the UK Government’s lifetime expenditure guarantee.

Click here to read more. 

Read more: http://www.powerbase-project.eu/project-work.html

May 2015 - May 2018

Recently Completed Projects


SPTS partnered with Swansea University’s School of Engineering and Medicine and Cardiff University  with support by the UK Technology Strategy Board in 2010 to commercialise tiny (micro and nano) devices in healthcare, communications and solar projects.

“Our project with Swansea University exposes us to new markets, technologists and other industries, such as pharmaceuticals.” Huma Ashraf, Process Manager (R&D Accounts), SPTS Technologies

Read more about the Microneedles program and it's progress in this article published in the British Journal of Dermatology

2010 - May 2017


eRAMP, lead by Infineon, includes 26 research partners from six countries. Including companies such as, Robert Bosch GmbH (Stuttgart, Germany), SGS INSTITUT FRESENIUS (Taunusstein, Germany), Siemens AG (Berlin, Munich), and many more. 

The objective of the three-year project “eRamp” is to strengthen and expand Germany and Europe as centers of expertise for the manufacture of power electronics. 

Read more: http://www.infineon.com/cms/en/product/promopages/eramp/

April 2014 - April 2017


The EPPL project received a total funding of 178k Euro. It included the involvement of companies such as AMS, Infineon, CEA Leti and SPTS. 

EPPL's main goal was to extend the leading position of power semiconductors “Made in Europe”. The expected improvements address both technical challenges and commercial competitiveness, in technology research, semiconductor manufacturing, chip/package interconnection technologies and energy efficient applications.

Read more: http://www.eppl-project.eu/impact/

April 2013 - April 2016


MAnufacturing Solutions Targeting competitive European pRoduction in 3D

Within Master 3D, SPTS Technologies, in collaboration with all the project partners (including, STMicro, Infineon, NXP, ams and others) proposed a Cost of Ownership (CoO) model and benefits for both via-middle and via-last packaging process flows. With CEA-LETI, SPTS demonstrated and characterized a CVD TiN  barrier layer deposition with excellent step coverage & electrical characterization on High Aspect Ratio TSV (up to 20:1) and demonstrated CoO benefits compared to conventional PVD methods. SPTS also worked with STMicro on the process development of Via-middle etching with 10:1 aspect ratio (10 µm vias / 100 µm deep) and achieved a high etching rate of >8 µm/min.

Click here to view the poster, presented at the Nanoelectronik Forum in Berlin 2015 

December 2012- December 2015