"Capabilities and Limits to Form High Aspect-Ratio Microstructures by Molding of Borosilicate Glass." A. Amnache et al

(Journal of Microelectromechanical Systems. Volume: 28 , Issue: 3 , pp432-440, June 2019 )

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"Dicing Tape Performance in a Plasma Dicing Environment" S. Fulton et al

(EPTC 2018)

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"Fan-Out Wafer Processing in the High Density Packaging Era" David Butler et al

(IWLPC 2018)

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"Characterization of Optical End-point Detection for Via Reveal Processing" N. Rassoul etc al

(ECTC2018)

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"MOCVD Copper Metallization for High Aspect Ratios TSV 3D Integration" S. Fadloun

(IMAPS 2018)
http://imapsource.org/doi/10.4071/2380-4505-2018.1.000718

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"UBM/RDL Deposition by PVD for FOWLP in High Volume Production" C. Jones

(ECTC 2018)

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"Plasma Dicing: Reducing the cost of singulating thinner, smaller die" O. Ansell

(iMAPS MINAPAD 2017)

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"Plasma Dicing 300mm Framed Wafers - Analysis of Improvement in Die Strength and Cost Benefits for for Thin Die Singulation" M. Blair

(ECTC 2017)

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"Characterization of Extreme Si Thinning Process for Wafer-to-Wafer Stacking" Inoue et al

(ECTC2016)

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"Impact of Backside Processing on C-V Characteristics of TSV Capacitors in 3D stacked IC Process flows" J. de Vos et al

(EPTC 2015)

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"Improving device yields and throughput using plasma dicing" R. Barnett et al

(IWLPC 2015)

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"Comparison between wet and dry silicon via reveal in 3D backside processing" D. Thomas et al; SPTS/imec joint paper

(IWLPC 2015)

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"Singulation by Plasma Etching. Integration Techniques to Enable Low Damage, High Productivity Dicing" R. Barnett et al

(ASME InterPACK2015)

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"Wafer-to-Wafer Metal Sputter Deposition Process Control by Automatic Deposition Rate Adjustment" C. Weng et al

(CS Mantech 2015)

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"Productivity Challenges in PVD Processing in 300mm Pilot Lines for Power Semiconductors" A Rastogi et al.

(ASMC 2015)

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"Development of an Optically Transparent Silicon Based Technology Platform for Biological Analysis" N Davies et al

(IEEE Sensors, Vol 15 No 3, pp1849-1857, Mar2015)

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"Extending Capabilities of Etch and Deposition Technologies for 3D Packaging of MEMS in Volume Production" C Short et al

(IWLPC2014)

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"Advances in Etch and Deposition Technologies for 2.5 and 3D BEOL Processing" K Buchanan et al

(SMTA Pan Pacific Symposium Conference 2014)

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"Claritas™ – A unique and robust endpoint technology for silicon DRIE processes with open area down to 0.05%" O. Ansell et al

(MEMS2014)

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"Considerations and Benefits of Plasma Etch Based Wafer Dicing" R. Barnett et al

(EPTC 2013)

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"Advances in Back-side Via Etching of SiC for GaN Device Applications" A. Barker et al

(CS Mantech 2013)

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"Dielectric Stack Engineering for Via-Reveal Passivation" K. Crook et al.

(ECTC 2013)

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"Low Temperature Dielectric Deposition for Via-Reveal Passivation" K. Crook et al.

(EMPC 2013)

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"Plasma Etch and Low Temperature PECVD Processes for Via Reveal Applications" D. Thomas et al

(ECTC 2012)

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"3D Multi-stacking of Thin Die based on TSV and Micro-inserts Interconnections" J. Souriau et al.

(ECTC 2012)

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